module stage_wb(
    input  wire[31:0]  wb_mem_data,
    input  wire[31:0]  wb_alu_o,
    input  wire        wb_mem2reg,
    output wire[31:0]  w_regs_data,
    input wire[31:0] wb_matrix_mopa_o[3:0],
    output wire[31:0] w_matrix_mopa[3:0]
);

assign w_regs_data = wb_mem2reg ? wb_mem_data : wb_alu_o;
assign w_matrix_mopa[0] = wb_matrix_mopa_o[0];
assign w_matrix_mopa[1] = wb_matrix_mopa_o[1];
assign w_matrix_mopa[2] = wb_matrix_mopa_o[2];
assign w_matrix_mopa[3] = wb_matrix_mopa_o[3];

endmodule
